(China (Mainland))
Product Summary
The H5TC4G83AFR-PBA is a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. The H5TC4G83AFR-PBA provides backward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.) The H5TC4G83AFR-PBA offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Parametrics
H5TC4G83AFR-PBA absolute maximum ratings: (1)VDD Voltage on VDD pin relative to Vss: -0.4 V ~ 1.80 V; (2)VDDQ Voltage on VDDQ pin relative to Vss: -0.4 V ~ 1.80 V; (3)VIN, VOUT Voltage on any pin relative to Vss: -0.4 V ~ 1.80 V; (4)TSTG Storage Temperature: -55 to +100°C.
Features
H5TC4G83AFR-PBA features: (1)DM masks write data-in at the both rising and falling edges of the data strobe; (2)All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock; (3)Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 supported; (4)Programmable additive latency 0, CL-1, and CL-2 supported; (5)Programmable CAS Write latency (CWL)= 5, 6, 7, 8, 9; (6)Programmable burst length 4/8 with both nibble sequential and interleave mode; (7)BL switch on the fly; (8)8banks; (9)JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16Driver strength selected by EMRS; (10)Dynamic On Die Termination supported; (11)Asynchronous RESET pin supported; (12)ZQ calibration supported; (13)TDQS (Termination Data Strobe)supported (x8 only); (14)Write Levelization supported; (15)8 bit pre-fetch.
Diagrams
