(China (Mainland))
Product Summary
The MT48LC16M16A2P-75ITD is a dynamic random-access memory, dynamic random-access memory containing 268,435,456 bits. The MT48LC16M16A2P-75ITD is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each of the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. The MT48LC16M16A2P-75ITD uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.
Parametrics
MT48LC16M16A2P-75ITD absolute maximum ratings: (1)Voltage on VDD; VDDQ supply relative to VSS: –1, +4.6 V; (2)Voltage on inputs, NC, or I/O pins relative to VSS: –1, +4.6 V; (3)Operating temperature TA (commercial): 0, +70℃; (4)Operating temperature TA (industrial “IT”): -40, +85℃; (5)Storage temperature (plastic): –55, +150 ℃; (6)Power dissipation: 1 W.
Features
MT48LC16M16A2P-75ITD features: (1)PC100- and PC133-compliant; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5 Programmable burst lengths: 1, 2, 4, 8, or full page; (6)Auto precharge, includes concurrent auto precharge, and auto refresh modes; (7)Self refresh mode; (8)64ms, 8,192-cycle refresh; (9)LVTTL-compatible inputs and outputs; (10)Single +3.3V ±0.3V power supply.
Diagrams
