Product Summary

The CY7C1412KV18-250BZXI is a 1.8 V synchronous pipelined SRAM, equipped with QDR II architecture QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port of the CY7C1412KV18-250BZXI has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

Parametrics

CY7C1412KV18-250BZXI absolute maximum ratings: (1)Storage temperature: -65℃ to +150℃; (2)Ambient temperature with power applied: -55℃ to +125℃; (3)Supply voltage on VDD relative to GND: -0.5 V to +2.9 V; (4)Supply voltage on VDDQ relative to GND: -0.5 V to +VDD; (5)DC applied to outputs in high Z: -0.5 V to VDDQ + 0.5 V; (6)DC input voltage[17]: -0.5 V to VDD + 0.5 V; (7)Current into outputs (LOW): 20 mA; (8)Static discharge voltage (MIL-STD-883, M. 3015): > 2001 V; (9)Latch-up current: > 200 mA.

Features

CY7C1412KV18-250BZXI features: (1)Separate independent read and write data ports, Supports concurrent transactions; (2)333 MHz clock for high bandwidth; (3)2-word burst on all accesses; (4)Double data rate (DDR) Interfaces on both read and write ports; (5)(data transferred at 666 MHz) at 333 MHz; (6)Two input clocks (K and K) for precise DDR timing, SRAM uses rising edges only; (7)Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches; (8)Echo clocks (CQ and CQ) simplify data capture in high speed systems; (9)Single multiplexed address input bus latches address inputs for both read and write ports; (10)Separate port selects for depth expansion; (11)Synchronous internally self-timed writes; (12)QDR. II operates with 1.5 cycle read latency when DOFF is asserted HIGH; (13)Operates similar to QDR I device with 1 cycle read latency when; (14)DOFF is asserted LOW; (15)Available in × 8, × 9, × 18, and × 36 configurations; (16)Full data coherency, providing most current data; (17)Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD, Supports both 1.5 V and 1.8 V I/O supply; (18)Available in 165-ball FBGA package (13 × 15 × 1.4 mm); (19)Offered in both Pb-free and non Pb-free Packages; (20)Variable drive HSTL output buffers; (21)JTAG 1149.1 compatible test access port; (22)Phase locked loop (PLL) for accurate data placement.

Diagrams

CY7C1412KV18-250BZXI block diagram

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