Product Summary

The GS88036BGT-200 is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the GS88036BGT-200 now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Parametrics

GS88036BGT-200 absolute maximum ratings: (1)VDD, Voltage on VDD Pins: -0.5 to 4.6 V; (2)VDDQ, Voltage in VDDQ Pins: -0.5 to 4.6 V; (3)VI/O, Voltage on I/O Pins: -0.5 to VDDQ +0.5 (≤ 4.6 V max.) V; (4)VIN, Voltage on Other Input Pins: -0.5 to VDD +0.5 (≤ 4.6 V max.) V; (5)IIN, Input Current on Any Pin: +/–20 mA; (6)IOUT, Output Current on Any I/O Pin: +/–20 mA; (7)PD, Package Power Dissipation: 1.5 W; (8)TSTG, Storage Temperature: -55 to 125℃; (9)TBIAS, Temperature Under Bias: -55 to 125℃.

Features

GS88036BGT-200 features: (1)FT pin for user-configurable flow through or pipeline operation; (2)Single Cycle Deselect (SCD) operation; (3)2.5 V or 3.3 V +10%/?0% core power supply; (4)2.5 V or 3.3 V I/O supply; (5)LBO pin for Linear or Interleaved Burst mode; (6)Internal input resistors on mode pins allow floating mode pins; (7)Default to Interleaved Pipeline mode; (8)Byte Write (BW) and/or Global Write (GW) operation; (9)Internal self-timed write cycle; (10)Automatic power-down for portable applications; (11)JEDEC-standard 100-lead TQFP package; (12)Pb-Free 100-lead TQFP package available.

Diagrams

GS88036BGT-200 block diagram