Product Summary

The K4T51043QG-ECE6 is a 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4banks or 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks device. The K4T51043QG-ECE6 achieves high speed doubledata-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency -1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.


K4T51043QG-ECE6 absolute maximum ratings: (1)Voltage on VDD pin relative to VSS, VDD: -1.0 ~ 2.3 V; (2)Voltage on VDDQ pin relative to VSS, VDDQ: -0.5 ~ 2.3 V; (3)Voltage on VDDL pin relative to VSS, VDDL: -0.5 ~ 2.3 V; (4)Voltage on any pin relative to VSS, VIN, VOUT: -0.5 ~ 2.3 V; (5)Storage Temperature, TSTG: -55 ~ 100℃.


K4T51043QG-ECE6 features: (1)JEDEC standard VDD = 1.8V ±0.1V Power Supply; (2)VDDQ = 1.8V ±0.1V; (3)200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin; (4)4 Banks; (5)Posted CAS; (6)Programmable CAS Latency: 3, 4, 5, 6; (7)Programmable Additive Latency: 0, 1 , 2 , 3, 4 , 5; (8)Write Latency(WL) = Read Latency(RL) -1; (9)Burst Length: 4 , 8(Interleave/Nibble sequential); (10)Programmable Sequential / Interleave Burst Mode; (11)Bi-directional Differential Data-Strobe (Single-ended datastrobe; (12)is an optional feature); (13)Off-Chip Driver(OCD) Impedance Adjustment; (14)On Die Termination; (15)Special Function Support, 50ohm ODT; High Temperature Self-Refresh rate enable; (16)Average Refresh Period 7.8us at lower than TCASE 85℃,; (17)3.9us at 85℃ < TCASE < 95℃; (18)All of products are Lead-Free, Halogen-Free, and RoHS compliant.


K4T51043QG-ECE6 block diagram