MT46V32M16-5B

Product Summary

The MT46V32M16-5B is a Double Data Rate (DDR) SDRAM. The MT46V32M16-5B uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the MT46V32M16-5B effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

Parametrics

MT46V32M16-5B absolute maximum ratings: (1)VDD supply voltage relative to VSS: –1V to +3.6V; (2)VDDQ supply voltage relative to VSS: –1V to +3.6V; (3)VREF and inputs voltage relative to VSS: –1V to +3.6V; (4)I/O pins voltage relative to VSS: –0.5V to VDDQ+ 0.5V; (5)Storage temperature (plastic): –55 to +150 °C; (6)Short circuit output current: – 50 mA.

Features

MT46V32M16-5B features: (1)VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V; (2)VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400); (3)Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte); (4)Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle; (5)Differential clock inputs (CK and CK#); (6)Commands entered on each positive CK edge; (7)DQS edge-aligned with data for READs; centeraligned with data for WRITEs; (8)DLL to align DQ and DQS transitions with CK; (9)Four internal banks for concurrent operation; (10)Data mask (DM) for masking write data (x16 has two – one per byte); (11)Programmable burst lengths: 2, 4, or 8; (12)Auto refresh: 64ms, 8192-cycle(Commercial and industrial), 16ms, 8192-cycle (Automotive); (13)Self refresh (not available on AT devices); (14)Longer-lead TSOP for improved reliability (OCPL); (15)2.5V I/O (SSTL_2 compatible); (16)Concurrent auto precharge option is supported; (17)tRAS lockout supported (tRAP = tRCD).

Diagrams