Product Summary

The MT48H16M32LFB5-75 is a 512Mb Mobile SDRAM. The MT48H16M32LFB5-75 is a high-speed CMOS, dynamic random-access memory containing 536,870,912-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1K columns by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as 8,192 rows by 512 columns by 32 bits. In a reduced page-size option, each of the x32’s 134,217,728-bit banks is organized as 16,384 rows by 256 columns x32 bits.

Parametrics

MT48H16M32LFB5-75 absolute maximum ratings: (1)Voltage on VDD/VDDQ supply relative to VSS: -0.3 to +2.7 V; (2)Voltage on inputs, NC or I/O balls relative to VSS: -0.3 to +2.7V; (3)Storage temperature plastic: -55 to +150℃; (4)Input leakage current: Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V), II: -1.0 to 1.0 μA.

Features

MT48H16M32LFB5-75 features: (1)Endur-IC technology; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)VDD = 1.7-1.95V; VDDQ = 1.7-1.95V; (4)Internal, pipelined operation; column address can be changed every clock cycle; (5)Four internal banks for concurrent operation; (6)Programmable burst lengths: 1, 2, 4, 8, and continuous1; (7)Auto precharge, includes concurrent auto precharge; (8)Auto refresh and self refresh modes; (9)LVTTL-compatible inputs and outputs; (10)On-chip temperature sensor to control refresh rate; (11)Partial-array self refresh (PASR); (12)Deep power-down (DPD); (13)Selectable output drive (DS).

Diagrams

MT48H16M32LFB5-75 block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)		 Quantity
MT48H16M32LFB5-75 IT:C
MT48H16M32LFB5-75 IT:C

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