(China (Mainland))
Product Summary
The MT48LC32M8A2P-75IT:D is a SDR SDRAM. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. The MT48LC32M8A2P-75IT:D provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
Parametrics
MT48LC32M8A2P-75IT:D absolute maximum ratings: (1)Voltage on VDD/VDDQ supply relative to VSS: -1 to 4.6 V; (2)Voltage on inputs, NC, or I/O balls relative to VSS: -1 to 4.6 V; (3)Storage temperature (plastic): -55 to 150 °C; (4)Power dissipation: 1 W.
Features
MT48LC32M8A2P-75IT:D features: (1)PC100- and PC133-compliant; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal, pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5)Programmable burst lengths: 1, 2, 4, 8, or full page; (6)Auto precharge, includes concurrent auto precharge and auto refresh modes; (7)Self refresh mode (not available on AT devices); (8)Auto refresh; (9)64ms, 8192-cycle refresh (commercial and industrial); (10)16ms, 8192-cycle refresh (automotive); (11)LVTTL-compatible inputs and outputs; (12)Single 3.3V+/-0.3V power supply.
Diagrams
