(China (Mainland))
Product Summary
The H5TQ1G83TFR-H9C is a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The H5TQ1G83TFR-H9C offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Parametrics
H5TQ1G83TFR-H9C absolute maximum ratings: (1)VDD, Voltage on VDD pin relative to Vss: - 0.4 V ~ 1.975 V; (2)VDDQ, Voltage on VDDQ pin relative to Vss: - 0.4 V ~ 1.975 V; (3)VIN, VOUT Voltage on any pin relative to Vss: - 0.4 V ~ 1.975 V; (4)TSTG, Storage Temperature: -55 to +100℃.
Features
H5TQ1G83TFR-H9C features: features: (1)VDD=VDDQ=1.5V +/- 0.075V; (2)Fully differential clock inputs (CK, CK) operation; (3)Differential Data Strobe (DQS, DQS); (4)On chip DLL align DQ, DQS and DQS transition with CK transition; (5)DM masks write data-in at the both rising and falling edges of the data strobe; (6)All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock; (7)Programmable CAS latency 6, 7, 8, 9, 10 supported; (8)Programmable additive latency 0, CL-1, and CL-2 supported; (9)Programmable CAS Write latency (CWL) = 5, 6, 7; (10)Programmable burst length 4/8 with both nibble sequential and interleave mode; (11)BL switch on the fly; (12)8banks; (13)Average Refresh Cycle; (14)Auto Self Refresh supported; (15)Driver strength selected by EMRS; (16)Dynamic On Die Termination supported; (17)Asynchronous RESET pin supported; (18) ZQ calibration supported; (19)TDQS (Termination Data Strobe) supported (×8 only); (20)Write Levelization supported; (21)8 bit pre-fetch.
Diagrams
