Product Summary

The H5TQ2G63BFR-PBC is a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The H5TQ2G63BFR-PBC offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Parametrics

H5TQ2G63BFR-PBC absolute maximum ratings: (1)VDD, Voltage on VDD pin relative to Vss: -0.4 V to 1.975 V; (2)VDDQ, Voltage on VDDQ pin relative to Vss: -0.4 V to 1.975 V; (3)VIN, VOUT Voltage on any pin relative to Vss: -0.4 V to 1.975 V; (4)TSTG, Storage Temperature: -55 to +100℃.

Features

H5TQ2G63BFR-PBC features: (1)VDD=VDDQ=1.5V +/- 0.075V (2)Fully differential clock inputs (CK, CK) operation (3)Differential Data Strobe (DQS, DQS) (4)On chip DLL align DQ, DQS and DQS transition with CK transition; (5)DM masks write data-in at the both rising and falling edges of the data strobe; (6)All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock; Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported (7)Programmable additive latency 0, CL-1, and CL-2 supported; Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10; Programmable burst length 4/8 with both nibble sequential and interleave mode; (8)BL switch on the fly; (9)Asynchronous RESET pin supported; (10)ZQ calibration supported; (11)TDQS (Termination Data Strobe) supported (x8 only); (12)Write Levelization supported; (13)8 bit pre-fetch.

Diagrams

H5TQ2G63BFR-PBC circuit diagram