(China (Mainland))
Product Summary
The K4H281638B-TCB0 is a 128Mb DDR SDRAM.
Parametrics
K4H281638B-TCB0 absolute maximum ratings: (1)Voltage on any pin relative to VSS, VIN, VOUT: -0.5 ~ 3.6 V; (2)Voltage on VDD supply relative to VSS, VDD, VDDQ: -1.0 ~ 3.6 V; (3)Voltage on VDDQ supply relative to VSS, VDDQ: -0.5 ~ 3.6 V; (4)Storage temperature, TSTG: -55 ~ +150℃; (5)Power dissipation, PD: 1.0 W; (6)Short circuit current, IOS: 50 mA.
Features
K4H281638B-TCB0 features: (1)Double-data-rate architecture; two data transfers per clock cycle; (2)Bidirectional data strobe(DQS); (3)Four banks operation; (4)Differential clock inputs(CK and CK); (5)DLL aligns DQ and DQS transition with CK transition; (6)MRS cycle with address key programs, Read latency 2, 2.5 (clock); Burst length (2, 4, 8); Burst type (sequential & interleave); (7)All inputs except data & DM are sampled at the positive going edge of the system clock(CK); (8)Data I/O transactions on both edges of data strobe; (9)Edge aligned data output, center aligned data input; (10)LDM,UDM/DM for write masking only; (11)Auto & Self refresh; (12)15.6us refresh interval(4K/64ms refresh); (13)Maximum burst refresh cycle: 8; (14)66pin TSOP II package.
Diagrams
