(China (Mainland))
Product Summary
The K4H510838C-UCCC is a 536,870,912 bits of double data rate synchronous DRAM. It is organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
Parametrics
K4H510838C-UCCC absolute maximum ratings: (1)Voltage on any pin relative to VSS: -0.5 to 3.6 V; (2)Voltage on VDD & VDDQ supply relative to VSS: -1.0 to 3.6 V; (3)Storage temperature: -55 to +150 °C; (4)Power dissipation: 1.5 W; (5)Short circuit current: 50mA.
Features
K4H510838C-UCCC features: (1)Double-data-rate architecture; two data transfers per clock cycle; (2)Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16); (3)Four banks operation; (4)Differential clock inputs(CK and CK); (5)DLL aligns DQ and DQS transition with CK transition; (6)MRS cycle with address key programs; (7).Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock); (8)All inputs except data & DM are sampled at the positive going edge of the system clock(CK); (9)Data I/O transactions on both edges of data strobe; (10)Edge aligned data output, center aligned data input; (11)LDM,UDM for write masking only (x16); (12)DM for write masking only (x4, x8); (13)Auto & Self refresh; (14)7.8us refresh interval(8K/64ms refresh); (15)Maximum burst refresh cycle : 8; (16)66pin TSOP II Pb-Free package; (17)RoHS compliant.
Diagrams
