(China (Mainland))
Product Summary
The LAN9500AC1107-A2P05 is a high performance Hi-Speed USB 2.0 hub with a 10/100 Ethernet controller. With applications ranging from embedded systems, desktop PCs, notebook PCs, printers, game consoles, and docking stations, the LAN9500AC1107-A2P05 is targeted as a high performance, low cost USB/Ethernet and USB/USB connectivity solution. The applications of the LAN9500AC1107-A2P05 include Desktop PCs, Notebook PCs, Printers, Game Consoles, Embedded Systems, Docking Stations.
Parametrics
LAN9500AC1107-A2P05 absolute maximum ratings: (1)Supply Voltage (VDD33IO, VDD33A): 0V to +3.6V; (2)Positive voltage on signal pins, with respect to ground: +6V; (3)Negative voltage on signal pins, with respect to ground: -0.5V; (4)Positive voltage on XI, with respect to ground: +4.6V; (5)Positive voltage on XO, with respect to ground: +2.5V; (6)Ambient Operating Temperature in Still Air (TA): Note 4.4; (7)Storage Temperature: -55℃ to +150℃; (8)Lead Temperature Range: Refer to JEDEC Spec. J-STD-020; (9)HBM ESD Performance per JESD 22-A114-E: +/- 8kV; (10)Contact Discharge ESD Performance per IEC61000-4-2: +/- 8kV; (11)Air-Gap Discharge ESD Performance per IEC61000-4-2: +/- 15kV; (12)Latch-up Performance per EIA/JESD 78: +/- 200mA.
Features
LAN9500AC1107-A2P05 features: (1)Fully compliant with Universal Serial Bus Specification Revision 2.0; (2)HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) compatible; (3)Two downstream ports, one upstream port; (4)Port mapping and disable support; (5)Port Swap: Programmable USB diff-pair pin location; (6)PHY Boost: Programmable USB signal drive strength; (7)Select presence of a permanently hardwired USB peripheral device on a port by port basis; (8)Advanced power saving features; (9)Downstream PHY goes into low power mode when port power to the port is disabled; (10)Full Power Management with individual or ganged power control of each downstream port.; (11)Integrated USB termination Pull-up/Pull-down resistors; (12)Internal short circuit protection of USB differential signal pins.
Diagrams
