MPC850DSLZQ50BU

MPC850DSLZQ50BU, one-chip integrated microprocessor, BGA, -0.3 to 4.0 V, 515mW, Freescale Semiconductor

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Price:: US $2.50~3.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
1 ~ 300 :	3.00 / Piece
301 ~ 600 :	2.80 / Piece
601 ~ 1000 :	2.50 / Piece

PartNumber:: MPC850DSLZQ50BU

Brand:: Freescale Semiconductor, Inc - Freescale | Pack: BGA | D/C: 11+

Availability:: Supply Ability: 1000/Day Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

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Products Upload time: 2013-05-07

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Part Number:MPC850DSLZQ50BU
US $2.50 - 3.00
Quantity:

piece

Product Summary

The MPC850DSLZQ50BU is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications, excelling particularly in communications and networking products. The MPC850DSLZQ50BU, which includes support for Ethernet, is specifically designed for cost-sensitive, remote-access, and telecommunications applications. It is provides functions similar to the MPC860, with system enhancements such as universal serial bus (USB) support and a larger (8-Kbyte) dual-port RAM.

Parametrics

MPC850DSLZQ50BU absolute maximum ratings: (1)Supply voltage VDDH: -0.3 to 4.0 V; VDDL: -0.3 to 4.0 V; KAPWR: -0.3 to 4.0 V; VDDSYN: -0.3 to 4.0 V; (2)Input voltage, Vin: GND-0.3 to VDDH +2.5 V; (3)Junction temperature, Tj: 0 to 95℃ (standard); -40 to 95 (extended)℃; (4)Storage temperature range, Tstg: -55 to +150℃.

Features

MPC850DSLZQ50BU features: (1)Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs), Performs branch folding and branch prediction with conditional prefetch, but without conditional execution; (2)2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture); Caches are two-way, set-associative; Physically addressed; Cache blocks can be updated with a 4-word line burst; Least-recently used (LRU) replacement algorithm; Lockable one-line granularity; (3)Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and fully-associative instruction and data TLBs; (4)MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and eight protection groups.