(China (Mainland))
Product Summary
THE H55S1222EFP-60M IS A 128MBit mobile SDR SDRAM based on 1M x 4Bank x32 I/O. The H55S1222EFP-60M is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs. The H55S1222EFP-60M is 134,217,728-bit CMOS mobile synchronous DRAM(mobile SDR), ideally suited for the main memory applications which requires large memory density and high bandwidth. The H55S1222EFP-60M is organized as 4banks of 1,048,576x32. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The H55S1222EFP-60M latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the data input/ output signals on a multiplexed x32 input/ output bus. All the commands are latched in synchronization with the rising edge of CLK.
Parametrics
H55S1222EFP-60M absolute maximum ratings: (1)Case temperature, TC: -25 to 85 ℃; -30 to 85 ℃; (2)Storage temperature, TSTG: -55 to 125 ℃; (3)Voltage on any pin relative to VSS, VIN, VOUT: -1.0 to 2.6 V; (4)Voltage on VDD relative to VSS, VDD: -1.0 to 2.6 V; (5)Voltage on VDDQ relative to VSS, VDDQ: -1.0 to 2.6 V; (6)Short circuit output current, IOS: 50 mA; (7)Power dissipation, PD: 1 W; (8)Soldering temperature . Time TSOLDER: 260 ℃. 20 Sec.
Features
H55S1222EFP-60M features: (1)Standard SDRAM protocol; (2)Clock synchronization operation: All the commands registered on positive edge of basic input clock (CLK); (3)Multibank operatiON - Internal 4bank operation: During burst read or write operation, burst read or write for a different bank is performed; During burst read or write operation, a different bank is activated and burst read or write for that bank is performed; During auto precharge burst read or write, burst read or write for a different bank is performed; (4)Power supply voltage : VDD / VDDQ = 1.7V to 1.95V; (5)LVCMOS compatible I/O interface; (6)Low voltage interface to reduce I/O power; (7)Programmable burst length: 1, 2, 4, 8 or full page; (8)Programmable burst type : sequential or interleaved; (9)Programmable CAS latency of 3 or 2.
Diagrams
