Product Summary

The MT47H256M8EB-25E:C is a DDR2 SDRAM. It uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. The MT47H256M8EB-25E:C provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

Parametrics

MT47H256M8EB-25E:C absolute maximum ratings: (1)VDD supply voltage relative to VSS: -1V to 2.3V; (2)VDDQ supply voltage relative to VSS: -0.5V to 2.3V; (3)VDDL supply voltage relative to VSSL; (4)Voltage on any ball relative to VSS: -0.5V to 2.3V; (5)Input leakage current; any input 0V <= VIN <= VDD; all other balls not under test = 0V): -5 to 5 uA.

Features

MT47H256M8EB-25E:C features: (1)VDD = 1.8V +/-0.1V, VDDQ = 1.8V +/-0.1V; (2)JEDEC-standard 1.8V I/O (SSTL_18-compatible); (3)Differential data strobe (DQS, DQS#) option; (4)4n-bit prefetch architecture; (5)Duplicate output strobe (RDQS) option for x8; (6)DLL to align DQ and DQS transitions with CK; (7)8 internal banks for concurrent operation; (8)Programmable CAS latency (CL); (9)Posted CAS additive latency (AL); (10)WRITE latency = READ latency - 1 tCK; (11)Programmable burst lengths: 4 or 8; (12)Adjustable data-output drive strength; (13)64ms, 8192-cycle refresh; (14)On-die termination (ODT); (15)Industrial temperature (IT) option; (16)RoHS-compliant; (17)Supports JEDEC clock jitter specification.

Diagrams

MT47H256M8EB-25E:C pin connection

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