Product Summary
The W9412G6JH-5 is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM); organized as 2M words × 4 banks × 16 bits. The W9412G6JH-5 delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the personal computer industrial standard, the W9412G6JH-5 is sorted into the following speed grades: -4, -5, -5I, -5K and -6I. The -4 is compliant to the DDR500/CL3 and CL4 specification.
Parametrics
W9412G6JH-5 absolute maximum ratings: (1)Voltage on any pin relative to VSS, VIN, VOUT: -0.5 ~ VDDQ + 0.5 V; (2)Voltage on VDD/VDDQ supply relative to VSS, VDD, VDDQ: -1 ~ 3.6 V; (3)Operating Temperature (-4/-5), TOPR: 0 ~ 70℃; (4)Operating Temperature (-5I/-6I), TOPR: -40 ~ 85℃; (5)Operating Temperature (-5K), TOPR: -40 ~ 105℃; (6)Storage Temperature, TSTG: -55 ~ 150℃; (7)Soldering Temperature (10s), TSOLDER: 260℃; (8)Power Dissipation, PD: 1 W; (9)Short Circuit Output Current, IOUT: 50 mA.
Features
W9412G6JH-5 features: (1)2.5V ±0.2V Power Supply for DDR400/333; (2)2.4V~2.7V Power Supply for DDR500; (3)Up to 250 MHz Clock Frequency; (4)Double Data Rate architecture; two data transfers per clock cycle; (5)Differential clock inputs (CLK and CLK ); (6)DQS is edge-aligned with data for Read; center-aligned with data for Write; (7)CAS Latency: 2, 2.5, 3 and 4; (8)Burst Length: 2, 4 and 8; (9)Auto Refresh and Self Refresh; (10)Precharged Power Down and Active Power Down; (11)Write Data Mask; (12)Write Latency = 1; (13)15.6μS Refresh interval (4K/64 mS Refresh), @ 0℃ ≤ TA ≤ 85℃; (14)3.9μS Refresh interval (4K/16 mS Refresh), @ 85℃< TA ≤ 105λ; (15)Maximum burst refresh cycle: 8; (16)Interface: SSTL_2; (17)Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant.
Diagrams
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W9412G6JH-5I |
IC DDR SDRAM 128MBIT 66TSOPII |
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W941232AD |
Other |
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Negotiable |
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W9412G6IH-5 |
IC DDR-400 SDRAM 128MB 66TSSOPII |
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Negotiable |
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W9412G6JH-5I |
IC DDR SDRAM 128MBIT 66TSOPII |
Data Sheet |
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